1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to the gate height uniformity of multiple finFET semiconductor devices.
2. Background of Invention
Dimensional uniformity of semiconductor device structures may be desired for optimal functionality. Dimensional variations can affect fabrication and ultimately the reliability of the semiconductor devices, for example finFET devices. Typical process flows used to fabricate finFET devices may produce large variations in gate height. The gate height can vary significantly within a single chip due to a variation in pattern density across the chip. An area of high pattern density may include a plurality of fins whereas an area of low pattern density may include one or two fins. Generally, the gate height measured in areas of low pattern density may be lower than the gate height measured in areas of high pattern density.
Typically, a gate first process flow may include forming fins in a substrate, depositing a gate stack including a high-k dielectric and one or more gate metals, and finally etching the final gate structures. Alternatively, a replacement gate (RG) process flow may include the use of a dummy gate stack. The thickness of the gate stack or the dummy gate stack may vary between areas of high pattern density and areas of low pattern density. It may be understood in the art that active areas may include areas of a chip where one or more semiconductor devices may be formed, whereas non-active areas may include areas of the chip free from semiconductor devices. Furthermore, active areas may have a higher pattern density (e.g. more fins) than non-active areas which may be free of fins.